Computer Architecture
How computers are built, from the instruction set down to digital logic, and how design decisions in pipelines, memory hierarchies, and parallel hardware determine performance.
A survey of how computer systems are designed: instruction set architecture, microarchitecture, digital logic, pipelined processor design, the memory hierarchy, and parallel processing.
Students will learn to:
- analyze how design decisions affect the performance of different processor designs;
- relate microarchitectures to the instruction set they implement;
- design digital circuits;
- understand instruction-level and processor-level parallelism.
Texts. Computer Organization and Design, RISC-V Edition: The Hardware/Software Interface (2nd ed.) by Patterson and Hennessy, with Robert Winkler’s RISC-V Assembly Programming.
Format. Lectures, discussion and in-class work (all graded work happens in class). Grading: assignments 35% · five quizzes 25% · two exams 40%.
Schedule 15
Week 1
Computer abstractions and technology
Week of Aug 18
abstractiontechnology trends
- Patterson & Hennessy, Chapter 1
Course overview (first class Aug 22)
Week 2
Performance analysis
Week of Aug 25
performancebenchmarking
- Patterson & Hennessy, Chapter 1
Assignment
Week 3
Instruction set architecture
Week of Sep 1
ISAassembly
- Patterson & Hennessy, Chapter 2
Assembly review · Quiz · Assignment
Week 4
RISC-V
Week of Sep 8
RISC-Vassembly programming
- Patterson & Hennessy, Chapter 2
- Winkler, RISC-V Assembly Programming
Assignment
Week 5
Digital logic
Week of Sep 15
gatescombinational logic
- Patterson & Hennessy, Appendix A
Quiz · Assignment
Week 6
Digital logic, continued
Week of Sep 22
sequential logic
- Patterson & Hennessy, Appendix A
Assignment
Week 7
Computer arithmetic
Week of Sep 29
integer arithmeticALU
- Patterson & Hennessy, Chapter 3
Quiz · Assignment
Week 8
Arithmetic, continued, and midterm review
Week of Oct 6
floating pointreview
- Patterson & Hennessy, Chapter 3
Assignment
Week 9
Midterm exam
Week of Oct 13
exam
Fall break follows
Week 10
Processor design and pipelining
Week of Oct 20
datapathpipelining
- Patterson & Hennessy, Chapter 4
Assignment
Week 11
Pipelining, continued
Week of Oct 27
hazardsforwarding
- Patterson & Hennessy, Chapter 4
Quiz · Assignment
Week 12
The memory hierarchy
Week of Nov 3
memory hierarchylocality
- Patterson & Hennessy, Chapter 5
Assignment
Week 13
Caches
Week of Nov 10
cachesvirtual memory
- Patterson & Hennessy, Chapter 5
Quiz · Assignment
Week 14
Parallel processing
Week of Nov 17
multicoreparallelism
- Patterson & Hennessy, Chapter 6
Assignment (week 15 was Thanksgiving)
Week 16
GPUs and final review
Week of Dec 1
GPUsreview
- Patterson & Hennessy, Chapter 6
Final exam Dec 8